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JULY 2000
PRELIMINARY
XRT95L51
OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
GENERAL DESCRIPTION
The XRT95L51 is an ATM/PPP physical layer processor with integrated SONET OC-48/STM-16 framing controller. ATM direct mapping and cell delineation are supported, as are PPP mapping and frame processing. The XRT95L51 contains an integral SONET framer which provides framing and error accumulation in accordance with ANSI/ITU-T specifications. The configuration of this device is done through internal registers accessible via 8-bit parallel, memory mapped, microprocessor interface. The XRT95L51 provides full section, line and path overhead processing and supports scrambling/descrambling, alarm signal insertion/detection and bit interleaved parity processing. The SONET/SDH transmit and receive blocks are used to transmit/receive an OC-48c/STM-16c signal or compose and decompose four OC-12/12c signals.The blocks operate at a peak internal clock speed of 77 MHz and support 32-bit internal data paths. The transmit and receive blocks are compliant with both SONET and SDH standards.
APPLICATIONS * Digital Cross Connect Systems * ATM Switches * Routers * SONET/SDH Add Drop Multiplexers * Multiplexers FEATURES * Single chip for ATM UNI and Packet over SONET. * Generates and terminates SONET section, line and path layers. * Provides SONET frame scrambling and descrambling. * Provides 32-bit data UTOPIA level II and III multiPHY interface and POS-PHY interface. * 8-bit microprocessor interface * Includes ATM cell or PPP packet mapping * Single +3.3V power supply with +5V input tolerance * -40C to +85C Operating Temperature Range * Available in a 388 pin PBGA package
FIGURE 1. BLOCK DIAGRAM OF THE 95L51 OC-48 ATM UNI/POS/MAPPER IC
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Microprocessor Interface
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7[72+&ON 7[72+(1% 7[72+ 7[72+,16 7[72+)3
Tx OC-12 Mapper X4
POH Generation & Insertion Tx ATM Cell Processor Tx POS Cell Processor Rx POS Cell Processor Rx ATM Cell Processor
Line Interface
Parallel to Serial Tx XCVR I/F
32
Tx Control
Serial to Parallel Rx XCVR I/F & Byte Align
32
Rx Framer SOH Processor POH Processor Descrambler
Rx Control Rx Cell Buffer
JTAG Test Port
Overhead Extraction Block
Rx OC-12 MapperX4
POH Extract & Interpret
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
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Utopia III ATM & POS I/F
Scrambler POH Processor SOH Processor Tx Framer
Tx Cell Buffer
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XRT95L51 OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
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PRELIMINARY
SONET/SDH RECEIVER * Performs standard STS-48c/STM-16c receive processing * Provides fully programmable threshold detection for SD and SF condition * Provides 155.52MHz 16-bit parallel interface * Provides section trace buffer with mis-match detection and invalid message detection * Performs SONET/SDH frame synchronization * Supports NDF, positive stuff and negative stuff pointer processor * Performs receive data de-scrambling * Performs POH,TOH interpretation/extraction * Interprets payload pointer (H1,H2) * Extracts data communication channels from D1-D3 and D4-D12 * Detects out of frame (OOF), loss of frame (LOF), loss of signal (LOS), APS failure * Detects Line Alarm Indication (L-AIS), Line remote Defect Indication (L-RDI), Loss of Pointer * Detects Path Alarm Indication, Path remote Defect Indication, Path extended RDI * Provides signal label monitor with PLM detection * Supports path travel buffer with TIM-P and invalid message detection * Computes and compare B3,REI-L and REI-P errors * Computes and compare BIP-8 (B1,B2) and counts the errors * Performs payload extraction. ATM CELL PROCESSOR * Implements the ATM physical layer for Broadband ISDN according to ITU-T Recommendation I.432 * Supports SDH mapping * Provides selectable on-going HEC insertion and verification * Provides selectable Coset addition and removal * Provides single bit error correction and multiple bit error detection for HEC processing * Provides HEC correctable and uncorrectable indications * Provides HEC correction selectability * Supports external cell GFC insertion and extraction * Provides the functions of cell rate de-coupling; idle cell insertion and detection, 16-cell FIFO cell buffering, programmable idle cell header and payload and idle cell HEC generation
FUNCTIONAL OVERVIEW XRT95L51 implements the SONET/SDH framing function with full duplex ATM/POS interface for the STS-48/STM-16 data streams.The XRT95L51 is functionally and architecturally, divided into the following blocks and modules: LINE SIDE INTERFACE * Differential inputs/outputs for high speed chip-tochip communication using Pseudo ECL logic. * Programmable parity bit for both incoming and outgoing data paths. * Monitors the Loss of Optical Carrier. * The transmit line side provides the direct looped back version of the line clock, framing pulse and parity. * The reference signal derived from the receive clock input can be programmed to be 77.76 MHz,38.88 MHz,19.44 MHz or 8 kHz. * The reference signal derived from the transmit clock input can be programmed to be 77.76 MHz,38.88 MHz, 19.44 MHz and 8 kHz. * 8 kHz reference signal can be phase locked to either incoming or outgoing SONET/SDH frame. * Supports Local and Remote Line Loopback. * Provides 155.52 MHz 16-bit parallel interface SONET/SDH TRANSMITTER * Performs standard OC-48c/STM-16c transmit processing * Conforms to IYU-T I.432,ANSI.105 and Bellcore GR-253 * Performs SONET/SDH frame insertion and accepts external frame synchronization * Performs optional transmit data scrambling * Performs POH,TOH generation/insertion * Generates transmit payload pointer (H1,H2) (fixed at 522) with NDF insertion * Inserts A1/A2 with optional error mask * Computes and inserts BIP-8 (B1,B2) with optional error mask * Generates AIS-L,REI-L and RDI-L according to receiver state with option of SW/HW insertion * Inserts LOS, forces SEF by software * Generates RDI-P and REI-P automatically with optional SW/HW override * Inserts fixed stuff columns, calculates and inserts B3 error code * Performs payload insertion from cell processor
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PRELIMINARY
* Offers cell delineation with three states (hunt, presync and sync) synchronization algorithm and provides LCD (Loss of Cell Delineation) indication and interrupt * Supports multiple programmable VPI/VCI filters on Transmit and Receive * Provides self-synchronizing SDH cell scrambling/ de-scrambling, x43+1 * Supports OAM cell insertion and extraction with dedicated cell store via microprocessor interface. Transmission is enabled through semaphore * Provides TXCell and TXCell indication signals * Provides test cell generation and verification PACKET OVER SONET (POS) PROCESSOR * Supports packet based link protocols by using byte synchronous HDLC framing like PPP ,HDLC and frame relay * 32-bit extended Saturn POS-PHY host interface clocked to 100 MHz * Performs transmit HDLC frame insertion and receive data extraction * Performs self-synchronous data scrambling and descrambling using1+X43 polynomial * Performs transmit flag sequence insertion and receive synchronization * Performs byte stuffing and de-stuffing for transparency processing * Performs optional CRC-CCITT and CRC-32 FCS generation and error checking * Supports optionally flow-through mode * Performs abort sequence insertion and detection * Arbitrary packet length (1 or more octets) and flag sharing (single flag between frames) * Provide minimum and maximum packet length checking, removing and reporting * Transparency by octet stuffing of flag (0x7E), control escape (0x7D) and abort sequence * Automatic transfer halt on receive FIFO host-side at end of packet * Error detection for Underflow of transmit FIFO, Overflow of receive FIFO, parity error on transmit * Optional removal of FCS from receive frames
XRT95L51
OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
* Optional transmit FCS insertion UTOPIA / POS-PHY INTERFACE * Complies with ATM forum Utopia Level 2 and 3 Specification * Supports 32-bit 100MHz Transmit and Receive interface * Provides up to total 16 cell buffers for transmit and receive * Transmits and receives both 52 and 54 byte cell * Generates and checks data parity of Utopia interface * Supports programmable Transmit CLAV (transmit cell available) signal for 0,1,2,3 cell look ahead * Supports programmable Receive CLAV (receive cell available) signal for 0,1,2,3 byte look ahead * Provides 32-bit up to 100 MHz industrial standard POS-PHY interface PERFORMANCE MONITORING * Supports line path performance monitoring * Provides 32-bit saturating counter of idle cells transmitted * Provides 32-bit saturating counter of assigned cells transmitted * Provides 32-bit saturating counter of valid cells received * Provides 32-bit saturating counter of idle cells received * Provides 32-bit saturating counter of cells received with HEC error * Provides 32-bit saturating counter of cells discarded * Provides 32-bit saturating counter of REI-L errors * Provides 32-bit saturating counter of REI-P errors * Provides 32-bit saturating counter of BIP-8 (B1,B2 and B3) errors * Provides 32-bit saturating counter of POS frame check sequence errors * Provides 32-bit saturating PPP good frame counter * Provides 32-bit saturating PPP bad FCS counter * Provides 32-bit saturating PPP aborted frame counter * Provides 32-bit saturating PPP Runt frame counter
3
XRT95L51 OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
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PRELIMINARY
FIFO under-run, change of cell alignment, HEC errors, LCD status change * Provides Local and Remote Line Loopback * Provides SONET Remote Loopback * Provides local ATM/PPP and UTOPIA Loopback * Supports IEEE 1149.1 JTAG testing
INTERRUPT, STATUS AND TEST * Provides individually maskable interrupts * Provides one second interrupt generations * Generates interrupts from the following causes: OOF status change, LOS status change, AIS status change, COFA, Utopia/PPP-PHY parity error, Utopia/PPP-PHY FIFO overrun, Utopia/PPP-PHY FIGURE 2. TYPICAL APPLICATION
Microprocessor
SONET Transmit Interface
Fiber Optic XCVR
SONET/SDH Line Interface 2.48Mb/s
Transmit
Utopia Level 3/ PPP 32-Bit Interface
Receive
OC-48/ STM-16 LIU
SONET Receive Interface
XRT95L51
EXAR OC-48/STM-16C Framer/Mapper
IP Router or ATM Switch
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PRELIMINARY
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ORDERING INFORMATION
PART NUMBER XRT95L51IB PACKAGE TYPE 388 Pin PBGA 35x35 mm, 26x26 Ball Matrix OPERATING TEMPERATURE RANGE -40C to +85C
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XRT95L51 OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
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PRELIMINARY
FIGURE 4. SIGNAL DIAGRAM OF XRT95L51
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PRELIMINARY
ORDERING INFORMATION
PART NUMBER XRT95L51IB PACKAGE TYPE
XRT95L51
OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
OPERATING TEMPERATURE RANGE -40C to +85C
388 Pin PBGA 35x35 mm, 26x26 Ball Matrix
PACKAGE DIMENSIONS
388 Ball Plastic Ball Grid Array (35 x 35 mm PBGA)
Rev. 1.0
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Chamfer Optional
b
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A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
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b A A1
A2
Symbol A A1 A2 b C D D1 D2 e
Inches MIN 0.075 0.020 0.039 0.024 0.016 1.370 MAX 0.106 0.028 0.051 0.035 0.028 1.386
Millimeters MIN MAX 1.90 0.50 1.00 0.60 0.40 34.80 2.70 0.70 1.30 0.90 0.70 35.20
1.250BSC 1.177 1.185 0.050BSC
31.75BSC 29.90 30.10 1.27BSC
Note: The control dimension is the millimeter column
7
XRT95L51
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OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
PRELIMINARY
REVISION HISTORY
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet July 2000. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 8

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